View EF6805U3_3657774.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

EF6805U3 march 1989 8-bit microcomputer unit . 32 ttl/cmos compatible i/o lines . 24 bidirectional (8 lines are led compati- ble) . 8 input-only . 3776 bytes of user rom . 112 bytes of ram . self-check mode . zero-crossing detect/interrupt . internal 8-bit timer with 7-bit soft- ware programmable prescaler and clock source . 5v single supply software features . 10 powerful addressing modes . byte efficient instruction set with true bit manipulation, bit test, and branch instructions . single instruction memory exa- mine/change . powerful indexed addressing for tables . full set of conditional branches . memory usable as register/flags . complete development system sup- port on inice user selectable options . 8 bidirectional i/o lines with ttl or ttl/cmos interface option . 8 bidirectional i/o lines with ttl or o- pen-drain interface option . crystal or low-cost resistor oscil- lator option . low voltage inhibit option . vectored interrupts : timer, soft- ware, and external . user callable self-check subrou- tines hardware features description the EF6805U3 microcomputer unit (mcu) is a member of the 6805 family of low-cost single-chip microcomputers. the 8-bit microcomputer contains a cpu, on-chip clock, rom, ram, i/o, and ti- mer. it is designed for the user who needs an eco- nomical microcomputer with the proven capabilities of the 6800-based instruction set. a comparison of the key features of several members of the 6805 fa- mily of microcomputers is shown at the end of this data sheet. the following are some of the hardware and software highlights of the EF6805U3 mcu. 1 pin connections fn (plcc 44) p (pdip40) 1/31
figure 1 : EF6805U3 hmos microcomputer block diagram. absolute maximum ratings symbol parameter value unit v cc supply voltage 0.3 to + 7.0 v v in input voltage (except timer in self-check mode and open-drain inputs) 0.3 to + 7.0 v v in input voltage (open-drain pins, timer pin in self-check mode) 0.3 to + 15.0 v t a operating temperature range v suffix t suffix (t l to t h ) 0to+70 40to+85 40to+105 c t stg storage temperature range 55 to + 150 c t j junction temperature plastic package plcc 150 150 c this device contains circuitry to protect the inputs against damage due to high static voltages or electrical fields, however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. for proper operation it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v cc . reliability of operation is en- hanced if unused inputs except extal are tied to an appropriate logic voltage level (e.g., either v ss or v cc ). thermal data q ja thermal resistance plastic plcc 50 80 c/w EF6805U3 2/31
power considerations the average chip-junction temperature, t j , in c can be obtained from : t j = t a + (p d .j a ) (1) where : t a = ambient temperature, c j a = package thermal resistance, junction-to-am- bient, c/w p d = p int + p port p int = i cc x v cc , watts - chip internal power p port = port power dissipation, watts - user de- termined for most applications p port p int and can be ne- glected. p port may become significant if the device is configured to drive darlington bases or sink led loads. an approximate relationship between p d and t j (if p port is neglected) is : p d = k + (t j + 273c) (2) solving equations 1 and 2 for k gives : k = p d .(t a + 273c) + j a .p d 2 (3) where k is a constant pertaining to the particular part. k can be determined from equation 3 by mea- suring p d (at equilibrium) for a known t a . using this value of k the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a . electrical characteristics (v cc = + 5.25vdc 0.5vdc, v ss = 0vdc, t a =t l to t h unless otherwise noted) symbol parameter min. typ. max. unit v ih input high voltage reset (4.75 v cc 5.75) (v cc < 4.75) int (4.75 v cc 5.75) (v cc < 4.75) all other (except timer) 4.0 v cc 0.5 4.0 v cc 0.5 2.0 v cc v cc v cc v cc v cc v v ih input high voltage timer timer mode self-check mode 2.0 9.0 10.0 v cc + 1.0 15.0 v v il input low voltage reset int all other v ss v ss v ss 0.8 1.5 0.8 v v ire s + v ire s reset hystereris voltages (see figures 10, 11 and 12) "out of reset" "into reset" 2.1 0.8 4.0 2.0 v v int int zero crossing input voltage, through a capacitor 24v ac p -p p d power dissipation - (no port loading, v cc = 5.75v) t a =0 c t a = 40 c 520 580 740 800 mw c in input capacitance extal all other 25 10 pf v lvr low voltage recover 4.75 v vl vi low voltage inhibit 2.75 3.75 4.70 v i in input current timer (v in = 0.4v) int (v in = 2.4v to v cc ) extal (v in = 2.4v to v cc - crystal option) (v in = 0.4v - crystal option) reset (v in = 0.8v) - external capacitor charging current 40.0 20 20 50 10 1600 ?0 m a * due to internal biasing this input (when unused) floats to approximately 2.2v. EF6805U3 3/31
switching characteristics (v cc = + 5.25vdc 0.5vdc, v ss = 0vdc, t a =t l to t h unless otherwise noted) symbol parameter min. typ. max. unit f osc oscillator frequency 0.4 4.2 mhz t cyc cycle time (4/f osc ) 0.95 10 m s t wl ,t wh int , int2 , and timer pulse width (see interrupt section) t cyc + 250 ns t rwl reset pulse width t cyc + 250 ns f int int zero-crossing detection input frequency 0.03 1 khz external clock input duty cycle (extal) 40 50 60 % crystal oscillator start-up time* 100 ms port electrical characteristics (v cc = + 5.25vdc 0.5vdc, v ss = 0vdc, t a =t l to t h unless otherwise noted) port a with cmos drive enabled symbol parameter min. typ. max. unit v ol output low voltage (i load = 1.6ma) 0.4 v v oh output high voltage i load = 100 m a i load = 10 m a 2.4 v cc 1.0 v v ih input high voltage (i load = 300 m a max.) 2.0 v cc v v il input low voltage (i load = 500 m a max.) v ss 0.8 v i ih high z state input current (v in = 2.0v to v cc ) 300 m a i il high z state input current (v in = 0.4v) 500 m a port b symbol parameter min. typ. max. unit v ol output low voltage i load = 3.2ma i load = 10ma (sink) 0.4 1.0 v v oh output high voltage i load = 200 m a 2.4 v i oh darlington current drive (source) v o = 1.5v 1.0 10 ma v ih input high voltage 2.0 v cc v v il input low voltage v ss 0.8 v i tsi high z state input current < 2 10 m a port c and port a with cmos drive disabled symbol parameter min. typ. max. unit v ol output low voltage i load = 1.6ma 0.4 v v oh output high voltage i load = 100 m a 2.4 v v ih input high voltage 2.0 v cc v v il input low voltage v ss 0.8 v i tsi high z state input current < 2 10 m s EF6805U3 4/31
figure 2 : ttl equivalent test load (port b). figure 3 : cmos equivalent test load (port a). figure 4 : ttl equivalent test load (port a andc). figure 5 : open-drain equivalent test load (port c). signal description the input and output signals for the mcu, shown in figure 1, are described in the following paragraphs. v cc and v ss - power is supplied to the mcu using these two pins. v cc is power and v ss is the ground connection. int - this pin provides the capability for asynchro- nously applying an external interrupt to the mcu. refer to interrupts section for additional informa- tion. xtal and extal - these pins provide control in- put for theon-chip clock oscillator circuit. a crystal, a resistor, or an external signal, depending on user selectable manufacturing mask option, can be connected to these pins to provide a system clock with various degrees of stability/cost tradeoffs. lead length and stray capacitance on these two pins should be minimized. refer to internal clock gen- erator options section for recommendations about these inputs. note : pin 7 in dil package/pin 8 in plcc package is connected to internal protection. timer - the pin allows an external input to be used to control the internal timer circuitry and also to ini- tiate the self test program. refer to timer section for additional information about the timer circuitry. reset - this pin allows resetting of the mcu at times other than the automatic resetting capability already in the mcu. the mcu can be reset by pul- ling reset low. refer to resets section for addi- tional information. EF6805U3 5/31
input/output lines (pa0-pa7, pb0-pb7, pc0- pc7, pd0-pd7) - these 32 liens are arranged into four 8-bit ports (a, b, c, and d). ports a, b, and c are programmable as either inputs or outputs under software control of the data direction registers (ddrs). port d is for digital input only and bit 6 may be used for a second interrupt int2. refer to in- put/output section and interrupts section for addi- tional information. memory - the mcu is capable of addressing 4096 bytes of memory and i/o registers with its program counter. the EF6805U3 mcu has implemented 4090 of these bytes. this consists of : 3776 user rom bytes, 192 self-check rom bytes, 112 user ram bytes, 7 port i/o bytes, 2 timer registers, and a miscellaneous register ; see figure 6 for the ad- dress map. the user rom has been split into two areas. the main user rom area is from $080 to $f37. the last 8 user rom locations at the bottom of memory are for the interrupt vectors. the mcu reserves the first-16 memory locations for i/o features, of which 10 have been implemented. these locations are used for the ports, the port ddrs, the timer and the int2 miscellaneous regis- ter, and the 112 ram bytes, 31 bytes are shared with the stack area. the stack must be used with care when data shares the stack area. the shared stack area is used during the processing of an interrupt or subroutine calls to save the contents of the cpu state. the register contents are pushed onto the stack in the order shown in figure 7. since the stack pointer decrements during pushes, the low order byte (pcl) of the program counter is stacked first, then the high order four bits (pch) are stacked. this ensures that the program counter is loaded correctly during pulls from the stack since the stack pointer increments when it pulls data from the stack. a subroutine call results in only the program counter (pcl, pch) contents being pushed onto the stack ; the remaining cpu re- gisters are not pushed. figure 6 : EF6805U3 mcu address map. * caution : data direction registers (ddrs) are write only, they read as $ff. EF6805U3 6/31
figure 6 : interrupt stacking order. central processing unit the cpu of the ef6805 family is implemented in- dependently from the i/o or memory configuration. consequently, it can be treated as an independent central processor communicating with i/o and me- mory via internal address, data, and control buses. registers the 6805 family cpu has five registers available to the programmer. they are shown in figure 8 and are explained in the following paragraphs. accumulator (a) - the accumulator is a general purpose 8-bit register used to hold operands and re- sults of arithmetic calculations or data manupula- tions. index register (x) - the index register is an 8- bit register used for the indexed addressing mode. it contains an 6-bit value that may be added to an instruction value to create an effective address. the index register can also be used for data manipula- tions using the read-modify-write instructions. the index register may also be used as a temporary storage area. figure 8 : programming model. program counter (pc) - the program coun- ter is a 12 bit register that contains th address of the next instruction to be executed. stack pointer (sp) - the stack pointer is a 12- bit register that contains the address of the next free location on the stack. during an mcu reset or the reset stack pointer (rsp) instruction, the stack poin- ter is set to location $07f. the stack pointer is then decremented as data is pushed onto the stack and incremented as data is then pulled from the stack. the seven most significant bits of the stack pointer are permanently set to 0000011. subroutines and interrupts may be nested down to location $061 (31 bytes maximum) which allows the programmer to use up to 15 levels of subroutine calls (less if inter- rupts are allowed). condition code register (cc) - the condi- tion code register is a 5-bit register in which foour bits are used to indicate the results of the instruction just executed. these bits can be individually tested by a program and specific action taken as a result of their state. each bit is explained in the following para- graphs. EF6805U3 7/31
half carry (h) - set during add and adc operations to indicate that a carry occurred between bits 3 and 4. interrupt (i) - when this bit is set, the timer an exter- nal interrupts (int and int2) are masked (disabled). if an interrupt occurs while this bit is set, the interrupt is latched and is processed as soon as the interrupt bit is cleared. negative (n) - when set, this bit indicates that the result of the last arithmetic, logical, or data manipu- lation was negative (bit 7 in the result is a logical "1"). zero (z) - when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. carry/borrow (c) - when set, this bit indicates that a carry or borrow ou of the arithmetic logic unit (alu) occurred during the last arithmetic operation. this bit is also affected during bit test and branch in- structions plus shifts and rotates. timer the timer circuitry for the EF6805U3 is shown in fig- ure 10. the timer contains a single 8-bit software programmable counter with a 7-bit software selec- table prescaler. the counter may be preset under program control and decrements toward zero. when the counter decrements to zero, the timer in- terrupt request bit, i.e., bit 7 of the timer control re- gister (tcr), is set. then if the timer interrupt is not masked, i.e.,bit 6 of the tcr and the i bit in the condition code register are both cleared, the proces- sor receives an interrupt. after completion of the cur- rent instruction, the processor proceeds to store the appropriate registers on the stack, and then fetches the timer interrupt vector from locations $ff8 and $ff9 in order to begin servicing the interrupt. the counter continues to count after it reaches zero, allowing the software to determine the number of in- ternal or external input clocks since the timer inter- rupt request bit was set. the counter may be read at any time by the processor without disturbing the count. the contents of the counter become stable prior to the read portion of a cycle and do not change during the read. the timer interrupt request bit re- mains set until cleared by the software. if a write oc- curs before the timer interrup is sericed, the interrupt is lost. tcr7 may also be used as a scanned status bit in a non-interrupt mode of operation (tcr6 = 1). the prescaler is a 7-bit divider which is used to ex- tend the maximum length of the timer. bit 0, bit 1, and bit 2 of the tcr are programmed to choose the appropriate prescaler outptu which is used as the counter input. the processor cannot writ eijto or read from the prescaler ; however, its contents are cleared to all zeros by the write operation into tcr when bit 3 of the written data equals one, which al- lows for truncation-free counting. the timer input can be configured for three different operating modes, plus a disable mode, depending on the value written to the tcr4 and tcr5 control bits. for further information see figure 9. timer input mode 1 - if tcr5 adn tcr4 are both programmed to a zero, the inpt to the timer is from an internal clock and the external timer input is di- sabled. the internal clock mode canbe used for pe- riodic interrupt generation, as well as a referene in frequency and event measurement. the internal clock is the instruction cycle clock. timer input mode 2 - with tcr5 = 0 and tcr4 = 1, the internal clock and the timer input pin are an- ded to form the timer input signal. this mode can be used to measure external pulse widths. the external timer input pulse simply turns on the internal clock for the duration of the pulse widths. timer input mode 3 - if tcr5 = 1 and tcr4 = 0, then all inputs to the timer are disabled. timer input mode 4 - if tcr5 = 1 and tcr4 = 1, the internal clock input to the timer is disabled and the timer input pin becomes the input to the timer. the external timer pin can, in this mode, be used to count external events as well as external frequen- cies for generating periodic interrupts. tcr7 - timer interrupt request bit : 76543210 tcr7 tcr6 tcr5 tcr4 tcr3 tcr2 tcr1 tcr0 $009 * write only (read as zero). 1 - set when tdr goes to zero, or under pro- gram control 0 - cleared on external reset, power-on-re- set, or under program control. tcr6 - timer interrupt mask bit : 1 - timer interrupt masked (disabled) set on external reset, power-on-reset, or under program control 0 - cleared under program control. tcr5 - external or internal clock source bit : 1 - external clock source. set on external re- set, power-on-reset, or under program control 0 - cleared under program control. tcr4 - external enable bit : 1 - enable external timer pin. set on external reset, poxer-on-reset, or under program EF6805U3 8/31
control. 0 - cleared under program control. tcr3 - timer prescaler reset bit : a read of tcr3 tcr5 tcr4 result 0 0 1 1 0 1 0 1 internal clock to timer and of internal clock and timer pin to timer input to timer disabled. timer pin to timer always indicates a zero. 1 - set on external reset, power-on-reset or under program control. 0 - cleared under program control tcr2 tcr1 tcr0 result 0 0 0 0 0 0 1 1 0 1 0 1 +1 +2 +4 +8 tcr2 tcr1 tcr0 result 1 1 1 1 0 0 1 1 0 1 0 1 +16 +32 +64 + 128 figure 9 : timer control register (tcr). tcr2 , tcr1, and tcr0 - prescaler address bits : 1 - all set on external reset, power-on-reset or under program control. 0 - cleared under program control. figure 10 : timer block diagram. notes : 1. prescaler and 8-bit counter are clocked on the failing edge of the internal clock (as) or external input. 2. counter is written to during dat strobe (ds) and counts down continuously. self-check - the self-check capability of the EF6805U3 mcu provides an internal check to de- termine if the part is functional. connect the mcu as shown in figure 11 and monitor the output of port c bit 3 for an oscillation of approximately 7hz. a 10- volt level (through a 10k resistor) on the timer input, pin 8 and pressing then releasing the reset but- ton, energizes the rom-based self-check feature. the self-check program exercices the ram, rom, timer, interrupts, and i/o ports. several of the self-check subroutines can be called by a user program with a jsr or bsr instruction. they are the ram, rom. the timer routine may also be called if the timer input is the internal 2 clock. to call those subroutines in customer application, please contact your local sgs-thomson micro- electronics sales office in order to obtain the complete description of the self-check program and the entrance/exit conditions. ram self-check subroutine - the ram self- check is called at location $f84 and returns with the z bit clear if any error is detected ; otherwise the z bit is set. the ram test causes each byte to count from 0 up to 0 again with a check after each count. the ram test must be called with the stack pointer at $07f and a = 0. when run, the test checks every ram cell except for $07f and $07e which are as- sumed to contain the return address. EF6805U3 9/31
the a and x registers and all ram locations except $07f and $07e are modified. rom checksum subroutine - the rom self- check is called at location $f95. the a register should be cleared before calling the routine. if any error is detected, it returns with the z bit cleared ; otherwise z = 1, x = 0 on return, and a is zero if the test passes. ram location $040 to $043 is overwrit- ten. the checksum is the complement of the execu- tion or of the contents of the user rom. * this connection depends on clock osc illator user selectable mask option. use jumper if the rc mask option is selected. figure 11 : self-check connections. led meanings pc0 pc1 pc2 pc3 remarks (1 : led on ; 0 : led off) 1 0 1 0 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 bad i/o bad timer bad ram bad rom bad interrupts or request flag all flashing good device EF6805U3 10/31
timer self-check subroutine - the timer self-check is called at location $f6d and returns with the z bit cleared if any error was found ; otherwise z = 1. in order to work correctly as a user subroutine, the internal 2 clock must be the clocking source and in- terrupts must be disabled. also, on exit, the clock is running and the interrupt mask is not set so the caller must protect from interrupts if necessary. the a and x register contents are lost. this routine sets the prescaler for divide-by-128 and the timer data register is cleared. the x register is configured to count down the same as the timer data register. the two registers are then compared every 128 cy- cles until they both count down to zero. any mis- match during the count down is considered as an er- ror. the a and x registers are cleared on exit from the routine. reset the mcu can be reset three ways : by initial powe- rup, by the external reset input (reset) and by an optional internal low-voltage detect circuit. the re- set input consists mainly of a schmitt trigger which senses the reset line logic level. a typical reset schmitt trigger hysteresis curve is shown in figure 12. the schmitt trigger provides an internal reset voltage if it senses a logical zero on the reset pin. power-on reset (por) - an internal reset is gene- rated upon powerup that allows the internal clock generator to stabilize. a delay of t rhl milliseconds is required before allowing the reset input to go high. refer to the power and reset timing diagram of figure 13. connecting a capacitor to the reset input (as illustrated in figure 14) typically provides sufficient delay. during powerup, the schmitt trigger switches on (removes reset) when reset rises to v ires+ . figure 12 : typical reset schmitt trigger hysteresis. figure 13 : power and reset timing. EF6805U3 11/31
figure 14 : reset configuration. external reset input - the mcu will be reset if a lo- gical zero is applied to the reset input for a period longer than one machine cycle (t cyc ). under this type of reset, the schmitt trigger switches off at v ires- to provide an internal reset voltage. low-voltage inhibit (lvi) - the optional low-voltage detection circuit causes a reset of the mcu if the po- wer supply voltage falls below a certain level (v lvi ). the only requirement is that v cc remains at or below the v lvi threshold for one t cyc minimum. in typical applications, the v cc bus filter capacitor will elimi- nate negative-going voltage glitches of less than one t cyc . the output from the low-voltage detector is connected directly to the internal reset circuitry. it al- so forces the reset pin low via a strong discharge device through a resistor. the internal reset will be removed once the power supply voltage rises above a recovery level (v lvr ), at which time a normal po- wer-on-reset occurs. internal clock generator options the internal clock generator circuit is designed to re- quire a minimum of external components. a crystal, a resistor, a jumper wire, or an external signal may be used to generate a system clock with various sta- bility/cost tradeoffs. the oscillator frequency is inter- nally divided by four to produce the internal system clocks. a manufacturing mask option is used to se- lect crystal or resistor operation. the different connection methods are shown in fig- ure 15. crystal specifications and suggested pc board layouts are given in figure 16. a resistor se- lection graph is given in figure 17. the crystal oscillator start-up time is a function of many variables : crystal parameters (especially r s ), oscillator load capacitances, ic parameters, am- bient temperature, and supply voltage. to ensure rapid oscillator start up, neither the crystal charac- teristics nor the load capacitances should exceed recommendations. when utilizing the on-board oscillator, the mcu should remain in a reset condition (reset pin voltage below v ires+ ) until the oscillator has stabilized at its operating frequency. several factors are involved in calculating the external reset capacitor required to satisfy this condition ; the oscillator start-up voltage, the oscillator stabilization time, the minimum v ires+ , and the reset charging current specification. once v cc minimum is reached, the external reset capacitor will begin to charge at a rate dependent on the capacitor value. the charging current is supplied from v cc through a large resistor, so it appears al- most like a constant current source until the reset voltage rises above v ires+ . therefore, the reset pin will charge at approximately : (v ires+ ).c ext = i res .t rhl assuming the external capacitor is initially dischar- ged. EF6805U3 12/31
figure 15 : clock generator options. note : the recommended cl value with a 4.0 mhz crystal is 27pf, maximum, including system distributed capacitance. there is an inter- nal capacitance of approximately 25pf on the xtal pin. for crystal frequencies other than 4mhz, the total capacitance on each p in should be scaled as the inverse of the frquency ratio. for example, with a 2mhz crystal, use approximately 50pf on extal and ap proxi- mately 25pf on xtal. the exact value depends on the motional-arm parameters of the crystal used. figure 16 : crystal motional arm parameters and suggested pc board layout. EF6805U3 13/31
figure 17 : typical frequency selection for resistor (oscillator option). interrupts the microcomputers can be interrupted four diffe- rent ways : through the external interrupt (int) input pin, the internal timer interrupt request, the external port d bit 6 (int2) input pin, or the software interrupt instruction (swi). when any interrupt occurs : the current instruction (including swi) is completed, processing is suspended, the present cpu state is pushed onto the stack, the interrupt bit (i) in the condition code register is set, the address of the in- terrupt routine is obtained from the appropriate in- terrupt vector address, and the interrupt routine is executed. stacking the cpu register, setting the i bit, and vector fetching require a total of 11 t cyc pe- riods for completion. a flowchart of the interrupt se- quence is shown in figure 18. the interrupt service routine must end with a return from interrupt (rti) instruction which allows the mcu to resume proces- sing of the program prior to the interrupt (by uns- tacking the previous cpu state). unlike reset, hardware interrupts do not cause the current in- struction execution to be halted, but are considered pending until the current instruction execution is complete. when the current instruction is complete, the pro- cessor checks all pending hardware interrupts and if unmasked, proceeds with interrupt processing ; otherwise the next instruction is fetched and execu- ted. note that masked interrupts are latched for later interrupt service. if both an external interrupt and a timer interrupt are pending at the end of an instruction execution, the external interrupt is serviced first. the swi is exe- cuted as any other instruction. EF6805U3 14/31
figure 18 : reset and interrupt processing flowchard. note the timer and int2 interrupts share the same vector address. the interrupt routine must determine the source by examining the interrupt request bits (tcr b7 and mr b7). both tcr b7 and mr b7 can only be written to zero by software. the external interrupt, int and int2, are synchro- nized and then latched on the falling edge of the in- put signal. the int2 interrupt has an interrupt re- quest bit (bit 7) and a mask bit (bit 6) located in the miscellaneous register (mr). the int2 interrupt is inhibited when the mask bit is set. the int2 is al- ways read as a digital input on port d. the int2 and timer interrup requests bits, if set, cause the mcu to process an interrupt when the condition code i bit is clear. a sinuoidal input signal (f int maximum) can be used to generate an external interrupt for use as a zero- crossing detector. this allows applications such as servicing time-of-day routines and engaging/disen- gaging ac power control devices. off-chip full wave rectification provides an interrupt at every zero cros- sing of the ac signal and thereby provides a 2f clock. see figure 19. note the int (pin 3) is internally biased at approximately 2.2v due to the internal zero-crossing detection. EF6805U3 15/31
a software interrupt (swi) is an executable instruc- tion which is executed regardless of the state of the i bit in the condition code register. swis are usually used as break-points for debugging or a system calls. figure 19 : typical interrupt circuits. input/output circuitry there are 32 input/output pins. the int pin may be polled with branch instructions to provide an additio- nal input pin. all pins on ports a, b, and c are pro- grammable as either inputs or outputs under soft- ware control of the corresponding data direction re- gister (ddr). see below i/o port control registers configuration. the port i/o programming is ac- complished by writing the corresponding bit in the port ddr to a logic one for output or a logic zero for input. on reset all the ddrs are initialized to a logic zero state, placing the ports in the input mode. the port output registers are not initialized on reset and should be initialized by software before changing the ddrs from input to output. a read operation on a port programmed as an output will read the contents of the output latch regardless of the logic levels at the output pin, due to output loading. refer to figure 20. port data register 7 0 port a addr = $000 port b addr = $001 port c addr = $002 port d addr = $003 port data direction register (ddr) 7 0 (1) write only ; reads as all 1s (2) 1 = output. 0 = input cleared to 0 by reset (3) port a addr = $004 port b addr = $005 port c addr = $006 EF6805U3 16/31
figure 20 : typical port i/o circuitry. data direction register bit latched output data bit output state input to mcu 1 1 0 0 1 x 0 1 high-z** 0 1 pin * ddr is a write-only register and reads as all "1s". ** ports b and c are three-state ports. port a has optional internal pull-up devices to provide cmos data drive capability. see electrical characteristic tables for complete in- formation. all input/output lines are ttl compatible as both in- puts and outputs. port a lines are cmos compatible as outputs (mask option) while port b, c, and d lines are cmos compatible as inputs. port d lines are in- put only ; thus, there is no corresponding ddr. when programmed as outputs, port b is capable of sinking 10 milliamperes and sourcing 1 milliampere on each pin. the address map (figure 6) gives the addresses of data registers and data direction registers. figure 21 provides some examples of port connections. caution the corresponding ddrs for ports a, b, and c are write-only registers (registers at $004, $005, $006 ). a read operation on these registers is undefined. since bset and bclr are read-modify-write in function, they cannot be used to set or clear a single ddr bit (all "unaffected" bits would be set). it is re- commended that all ddr bits in a port be written u- sing a single-store instruction. the latched output data bit (see figure 20) must al- ways be written. therefore, any write to a port writes all of its data bits even though the port ddr is set to input. this may be used to initialize the data re- gister and avoid undefined outputs ; however, care must be exercised when using read-modify-write in- structions, since the data read corresponds to the pin level if the ddr is an input (zero) and corre- sponds to the latched output data when the ddr is an output (one). EF6805U3 17/31
figure 21 : typical port connections. EF6805U3 18/31
software bit manipulation the EF6805U3 mcu has the ability to set or clear any single random access memory or input/output bit (except the data direction register, see caution below), with a single instruction (bset, bclr). any bit in page zero including rom, except the ddrs, can be tested, using the brset and brclr ins- tructions, and the program branches as a result of its state. the carry bit equals the value of the bit ref- erenced by brset or brclr. a rotate instruction may then be used to accumulate serial input data in a ram location or register. the capability to work with any bit in ram, rom, or i/o allows the user to have individual flags in ram or to handle i/o bits as control lines. the coding example in figure 21 illustrates the use- fulness of the bit manipulation and test instructions. assume that the mcu is to communicate with an ex- ternal serial device. the external device has a data ready signal, a data output line, and a clock line to clock data one bit at a time. lsb first, out of the device. the mcu waits until the data is ready, clocks the external device, picks up the data in the carry flag (c bit), clears the clock line, and finally accumulates the data bit in a ram location. caution the corresponding ddrs for ports a, b, and c are write-only registers (registers at $004, $005, and $006). a read operation on these registers is undefined. since bset and bclr are read- modify-write functions, they cannot be used to set or clear a ddr bit (all "unaffected" bits would be set). it is recommended that all ddr bits in a port be written using a single-store instruction. figure 21 : bit manipulation example. addressing modes the ef6805p2 mcu has 10 addressing modes which are explained briefly in the following para- graphs. for additional details and graphical illustra- tions, refer to the 6805 family user's manual. the term "effective address" (ea) is used in descri- bing the address modes. ea is defined as the ad- dress from which the argument for an instruction is fetched or stored. immediate - in the immediate addressing mode, the operand is contained in the byte immediately fol- lowing the opcode. the immediate addressing mode is used to access constants which do not change during program execution (e.g;, a constant used to initialize a loop counter). direct - in the direct addressing mode, the effec- tive address of the argument is contained in a single byte following the opcode byte. direct addresing al- lows the user to directly address the lowest 256 bytes in memory with a single 2-byte instruction. this includes the on-chip ram and i/o registers and 128 bytes of rom. direct addressing is an effective use of both memory and time. extended - in the extended addressing mode, the effective address of the argument is contained in the two bytes following the opcode. instructions using extended addressing are capable of referencing ar- guments anywhere in memory with a single 3-byte instruction. when using the motorola assembler, the programmer need not specify whether an instruction uses direct or extended addressing. the assembler automatically selects the shortest for of the instruc- tion. relative - the relative addressing mode is only used in branch instructions. in relative addressing, the contents of the 8-bit signed byte following the op- code (the offset) is added to the pc if and only if the EF6805U3 19/31
branch condition is true. otherwise, control pro- ceeds to the next instruction. the span of relative addressing is from - 126 to + 129 from the opcode address. the programmer need not worry about cal- culating the correct offset when using the motorola assembler since it calculates the proper offset and checks to see if it is within the span of the branch. indexed, no offset - in the indexed, no offset addressing mode, the effective address of the argu- ment is contained in the 8-bit index register. thus, this addressing mode can access the first 256 me- mory locations. these instructions are only one byte long. this mode is often used to move a pointer through a table or to hold the address of a frequently referenced ram or i/o location. indexed, 8-bit offset - in the indexed, 8-bit off- set addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index re- gister and the unsigned byte following the opcode. this addressing mode is useful in selecting the kth element in an n element table. with this 2-byte ins- truction, k would typically be in x with the address of the beginning of the table in the instruction. as such, tables may begin anywhere within the first 256 addressable locations and could extend as far as lo- cation 510 ($1fe is the last location at which the ins- truction may begin). indexed, 16-bit offset - in the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index re- gister and the two unsigned bytes following the op- code. this addressing mode can be used in a man- ner similar to indexed, 8-bit offset, except that this 3-byte instruction allows tables to be anywhere in memory. as with direct and extended addressing, the motorola assembler determines the shortest form of indexed addressing. bit set/clear - in the bit set/clear addressing mode, the bit to be set or cleared is part of the op- code, and the byte following the opcode specifies the direct address of the byte in which the specified bit is to be set or cleared. thus, any read/write bit in the first 256 locations of memory, including i/o, can be selectively set or cleared with a single 2-byte ins- truction. caution the corresponding ddrs for ports a, b, and c are write-only registers (registers at $004, $005, and $006). a read operation on these registers is undefined. since bset and bclr are read- modify-write functions, they cannot be used to set or clear a ddr bit (all "unaffected" bits would be set). it is recommended that all ddr bits in a port be written using a single-store instruction. bit test and branch - the bit test and branch addressing mode is a combination of direct addres- sing and relative addressing. the bit and condition (set or clear) which is to be tested is included in the opcode, and the address of the byte to be tested is in the single byte immediately following the opcode byte. the signed relative 8-bit offset is in the third byte and is added to the value of the pc if the branch condition is true. this single 3-byte instruction allows the program to branch based on the condition of any readable bit in the first 256 locations of memory. the span of branching is from - 125 to + 130 from the op- code address. the state of the tested bit is also transferred to the carry bit of the condition code re- gister. caution the corresponding ddrs for ports a, b, and c are write-only registers (registers at $004, $005, and $006). a read operation on these registers is undefined. since bset and bclr are read- modify-write functions, they cannot be used to set or clear a ddr bit (all "unaffected" bits would be set). it is recommended that all ddr bits in a port be written using a single-store instruction. inherent - in the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. operations specifying only the index register or accumulator, as well as control instruction with no other arguments, are in- cluded in this mode. these instructions are one byte long. instruction set the EF6805U3 mcu has a set of 59 basic instruc- tions, which when combined with the 10 addressing modes produce 207 usable opcodes. they can be divided into five different types : register/memory, read-modify-write, branch, bit manipulation, and control. the following paragraphs briefly explain each type. all the instructions within a given type are presented in individual tables. register/memory instructions - most of these instructions use two operands. one operand is either the accumulator or the index register. the other operand is obtained from memory using one of the addressing modes. the jump unconditional (jmp) and jump to subroutine (jsr) instructions have no register operands. refer to table 1. read-modify-write modifications - these instructions read a memory location or a register, EF6805U3 20/31
modify or test its contents, and write the modified va- lue back to memory or to the register. the test for negative or zero (tst) instruction is included in read-modify-write instructions through it does not perform the write. rfer to table 2. caution the corresponding ddrs for ports a, b, and c are write-only registers (registers at $004, $005, and $006). a read operation on these registers is undefined. since bset and bclr are read- modify-write functions, they cannot be used to set or clear a ddr bit (all "unaffected" bits would be set). it is recommended that all ddr bits in a port be written using a single-store instruction. branch instructions - the branch instruc- tions cause a branch from the program when a cer- tain condition is met. refer to table 3. bit manipulation instructions - these ins- tructions are used on any bit in the first 256 bytes of the memory. one group either sets or clears. the o- ther group performs the bit test branch operations. refer to table 4. caution the corresponding ddrs for ports a, b, and c are write-only registers (registers at $004, $005, and $006). a read operation on these registers is undefined. since bset and bclr are read- modify-write functions, they cannot be used to set or clear a ddr bit (all "unaffected" bits would be set). it is recommended that all ddr bits in a port be written using a single-store instruction. control instructions - the control instruc- tions control the mcu operations during program execution. refer to table 5. alphabetical listing - the complete instruc- tion set is given in alphabetical order in table 6. opcode map summary - table 7 is an opcode map for the instructions used on the mcu. EF6805U3 21/31
table 1 : register/memory instructions. EF6805U3 22/31
table 2 : read-modify-write instructions. EF6805U3 23/31
table 3 : branch instructions . relative addressing mode function mnemonic op code # bytes # cycles branch always bra 20 2 4 branch never brn 21 2 4 branch iff higher bhi 22 2 4 branch iff lower or same bls 23 2 4 branch iff carry clear bcc 24 2 4 (branch iff higher or same) (bhs) 24 2 4 branch iff carry set bcs 25 2 4 (branch iff lower) (blo) 25 2 4 branch iff not equal bne 26 2 4 branch iff equal beq 27 2 4 branch iff half carry clear bhcc 28 2 4 branch iff half carry set bhcs 29 2 4 branch iff plus bpl 2a 2 4 branch iff minus bmi 2b 2 4 branch iff interrupt mask bit is clear. bmc 2c 2 4 branch iff interrupt mask bit is set. bms 2d 2 4 branch iff interrupt line is low. bil 2e 2 4 branch iff interrupt line is high. bih 2f 2 4 branch to subroutine bsr ad 2 8 table 4 : bit manipulation instructions. addressing modes bit set/clear bit test and branch function mnemonic op code # bytes # cycles op code # bytes # cycles branch iff bit n is set brset n (n = 0 7) 2 n 3 10 branch iff bit n is clear brclr n (n = 0 7) 01 + 2 n 310 set bit n bset n (n = 0 7) 10 + 2 n 27 clear bit n bclr n (n = 0 7) 11 + 2 n 27 EF6805U3 24/31
table 5 : control instructions. inherent function mnemonic op code # bytes # cycles transfer a to x tax 97 1 2 transfer x to a txa 9f 1 2 set carry bit sec 99 1 2 clear carry bit clc 98 1 2 set interrupt mask bit sei 9b 1 2 clear interrupt mask bit cli 9a 1 2 software interrupt swi 83 1 11 return from s ubroutine rts 81 1 6 return from interrupt rti 80 1 9 reset stack pointer rsp 9c 1 2 no-operation nop 9d 1 2 table 6 : instruction set. addressing modes condition code mnem inherent immediate direct extended relative indexed (no offset) indexed (8 bits) indexed (16 bits) bit set/clear bit test & branch hinzc adc x x x x x x l add x x x x x x l and x x x x x x ll l asl x x x x ll asr x x x x ll bcc x lllll bclr x lllll bcs x lllll beq x lllll bhcc x lllll bhcs x lllll bhi x lllll bhs x lllll bih x lllll bil x lllll bit x x x x x x ll l blo x lllll bls x lllll bmc x lllll bmi x lllll bms x lllll bne x lllll bpl x lllll bra x lllll brn x lllll brclr x llll brset x llll bset x lllll bsr x lllll cll x llll 0 EF6805U3 25/31
table 6 : instruction set (continued). addressing modes condition code mnem inherent immediate direct extended relative indexed (no offset) indexed (8 bits) indexed (16 bits) bit set/clear bit test & branch hinzc cli x l 0 lll clr x x x x ll 01 l cmp x x x x x x ll com x x x x ll 1 cpx x x x x x x ll dec x x x x ll l eor x x x x x x ll l inc x x x x ll l jmp x x x x x lllll jsr x x x x x lllll lda x x x x x x ll l ldx x x x x x x ll l lsl x x x x ll lsr x x x x ll 0 neq x x x x ll nop x lllll ora x x x x x x ll l rol x x x x ll rsp x lllll rti x ????? rts x lllll sbc x x x x x x ll sec x llll 1 sei x l 1 lll sta x x x x x ll l stx x x x x x ll l sub x x x x x x ll swi x l 1 lll tax x lllll tst x x x x ll l txa x lllll condition code symbols : h half carry (from bit 3) i interrupt mask n negative (sign bit) z c ^ test and set if true, cleared otherwise not affected EF6805U3 26/31
hmos 6805 family features ef6805p2 ef6805p6 ef6805r2 ef6805r3 ef6805u2 EF6805U3 technology hmos hmos hmos hmos hmos hmos number of pins 28 28 40 40 40 40 on-chip ram (bytes) 64 64 64 112 64 112 on-chip user rom (bytes) 1100 1796 2048 3776 2048 3776 external bus none none none none none none bidirectional i/o lines 20 20 24 24 24 24 unidirectional i/o lines none none 6 inputs 6 inputs 8 inputs 8 inputs other i/o features timer timer timer, a/d timer, a/d timer timer external interrupt inputs 112222 stop and wait no no no no no no EF6805U3 27/31
table 7 : 6805 hmos family opcode map. EF6805U3 28/31
package mechanical data 40 pin plastic dual in line package (pdip) 44 pin plastic quad package (plcc) dim. mm inches min typ max min typ max a 2.2 4.8 0.086 0.189 a1 0.51 1.77 0.010 0.069 b 0.38 0.58 0.015 0.023 b1 0.97 1.52 0.055 0.065 c 0.2 0.3 0.008 0.009 d 50.30 52.221.980 20.56 d1------ e 16.3 0.641 e1 12.9 0.508 k1CCCCCC k2CCCCCC l 3.18 4.44 1.25 0.174 e1 2.54 0.10 number of pins n40 dim. mm inches min typ max min typ max a 4.2 5.08 0.165 0.200 a1 0.64 0.020 a3 2.29 3.30 0.090 0.130 b 0.331 - - - - - b1 0.661 - - - - - d 17.40 17.650.685 0.695 d1 16.51 16.660.650 0.656 d3 12.70 0.500 e 17.40 17.650.685 0.695 e1 16.51 16.660.650 0.656 e3 12.70 0.500 k1------ e 1.27 0.050 number of pins n44 nd 11 EF6805U3 29/31
ordering information the information required when ordering a custom mcu is listed below. the rom program may be transmitted to sgs-thomson on eprom(s) or an efdos/mdos* disk file. to initiate a rom pattern for the mcu, it is neces- sary to first contact your local sgs-thomson re- presentative or distributor. eproms one 2716 or 2732 type eproms, programmed with the customer program (positive logic sense for ad- xxx = customer id) dress and data), may be submitted for pattern ge- neration. after the eprom is marked, it should be placed in conductive ic carriers and securely packed. do not use styrofoam. verification media all original pattern media (eproms or floppy disk) are filed for contractual purposes and are not retur- ned. a computer listing of the rom code will be ge- nerated and returned along with a listing verification form. the listing should be thoroughly checked and the verification form completed, signed, and retur- ned to sgs-thomson. the signed verification form constitutes the contractual agreement for crea- tion of the customer mask. if desired, sgs-thom- son will program on blank eprom from the data file used to create the custom mask and aid in the verification process. rom verification units (rvus) ten mcus containing the customer's rom pattern will be sent for program verification. these units will have been made using the custom mask but are for the purpose of rom verification only. for expedien- cy they are usually unmarked, packaged in ceramic, and tested only at room temperature and 5 volts. these rvus are included in the mask change and are not production parts. the rvus are thus not guaranteed by sgs thomson. quality assu- rance, and should be discarded after verification is completed. flexible disks the disk media submitted must be single-sided, ef- dos/mdos* compatible floppies. the customer must write the binary file name and company name on the disk with a felt-tip-pen. the minimum efdos/mdos* system files, as well as the absolute binary object file (filename .lo type of file) from the 6805 cross assembler, must be on the disk. an object file made from a memory dump using the rollout command is also acceptable. consi- der submitting a source listing as well as the follo- wing files : filename .lx (device/exorciser loada- ble format) and filename .sa (ascii source code). these files will of course be kept confidential and are used 1) to speed up the process in-house if any pro- blems arise, and 2) to speed up the user-to-factory interface if the user finds any software errors and needs assistance quickly from sgs-thomson factory representatives. efdos is sgs-thomson disk operating system available on development systems such as de- vice... mdos* is motorola's disk operating system available on development systems such as exor- ciser... * requires prior factory approval. whenever ordering a custom mcu is required, please contact your local sgs-thomson representative or sgs-thomson distributor and/or complete and send the attached "mcu customer ordering sheet" to your local sgs-thomson microelectronics representative. EF6805U3 30/31
device package oper. temp. screening level c j p e fn l* v t std d g/b b/b EF6805U3 x xxxxxx examples : EF6805U3p, EF6805U3fn, EF6805U3pv, EF6805U3fnv order codes EF6805U3 p v device package screen level oper. temp. the table below horizontally shows all available suffix combinations for package, operating temperature and screening level. other possibilities on request. package : c : ceramic dil, j : cerdip dil, p : plastic dil, e : lccc, fn : plcc oper. temp. : l* : 0?c to + 70?c, v : C 40 ?c to + 85?c, t : C 40?c to + 105?c, * : may be omitted. screening level : std : (no-end suffix), d : nfc 96883 level d, exorciser is a registered trademark of motorola inc. information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved. purchase of i 2 c components by sgs-thomson microelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco the netherlands - singap ore - spain sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. EF6805U3 31/31

▲Up To Search▲

Price & Availability of EF6805U3

	To Download EF6805U3 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .